2015 ● For the first time, low cost self-powered chip for Internet of Things was realized by hetero-integrated TSV-free monolithic 3D-IC and
ambient light energy harvester.
● Hosted the SemiconNano 2015, near 100 scholars and experts from
all over the world were invited to discuss the latest trends
regarding nano technology.
● Published 6 papers during the International Electron
Devices Meeting(IEDM), 2 of which were selected as highlight papers.
The NDL team was among the leading teams in the number of
papers published during the meeting, including IMEC (15 papers),
IBM (9 papers), TSMC (7 papers), and Intel (4 papers).

2014 ● With the innovative Monolithic 3D-IC technology, each stacking layer is
thinner than the conventional counterpart by nearly 150 times,
which enables significantly faster signal transmission and lower power
consumption compared to the 3D-IC made with TSV.
● Novel Junction-less Field-Effect Transistors, super shallow
doping technology involving molecular self-assembly produces novel
junction-less FETs.
● Application of Sub-10 nm 2D Electronic Channel Materials to 3D FETs,
they make the way for the production of 2D N-type elements with
driving currents in excess of 25%.

2013 ● “Industry-Academy Alliance for Nano Device Innovation” was set up.
● Dual Fin Height FinFET was developed to reduce area of embedded SRAM chip by 20%.
● l Nano point memory technology was innovated with 10 to 100 times faster than the popular
    mainstream charge storage memory products.
● High efficiency CIGS solar cell process service platform with conversion efficiency up to 10%
    was accomplished.

2012 ● “Rapid Assessment Technology for Rare Pathogenic Bacteria in Blood” was awarded with
    “9th National Innovation Award”

2011 ● Led the world to develop highly applicable “Self Powered Circuit Module Silicon Based Solar
    Device” successfully.
● The “triangular germanium FinFET”, which can improve operation speed of silicon planar
    transistors by 2 to 4 times, is developed.
● “Silver metal vertical lead technology” broke through the bottleneck of conventional wu
    metal plug structure process.

2010 ● The worldwide smallest 9 nanometer functional resistive memory (R-RAM) array cell was
    developed.
● The nationwide first SOI and 1P4M CMOS-MEMS R&D platform system developed by
    academic research unit was accomplished.

2009 ● The worldwide first 16 nanometer functional SRAM unit cell was completed.
● The worldwide first “non-current driven silicon quantum point” storage device was
    completed.
● The low temperature microwave annealing activation process was utilized to complete the first
    transistor which was activated at a temperature below 320℃.

2008 ● The first worldwide silicon based ferroelectric memory was completed.

2007 ● The Southern Office was located in Chimei Building, NCKU (National Cheng Kung University),
    and NCKU signed to cooperate for development of nano energy and research program of solar
    cell.
● l Non optical disturbance electrical scan probe microscopy was developed successfully with the
    self-developed front-wing cantilever conductive probe.
● ISO/IEC 17025 certification was approved to provide standard, accurate and rapid material
     analysis and detection services.

2006 ● l “UMC-NDL Young Scholar Grant Cooperation Agreement” was signed with UMC to
    cultivate national nano device elite talents.
● ISO 9001:2000 quality management system certification was approved to improve process
    technology autonomous operation and talent cultivation service quality.

2005 ● “Wafer Level High Frequency Device Automatic Test and Analysis Technology Cooperation
    Agreement” was signed with Agilent Technology to determine mutual long-term cooperation
    relationship in order to improve Taiwan semiconductor industry together.

2004 ● “Nano Electronics Research Building” was constructed completely.

2004 ● Change to be affiliated with “National Applied Research Laboratories”

  ● Renamed to “National Nano Device Laboratories”
● Southern Office was set up in Tainan Science Park to create semiconductor research
    environment in adaptation to the national south-north balance policy.

1995 ● The five-year development program (1998 ~ 2003) was planned with respect to 250nm device
    technology.

1994 ● The 250nm device technology was under development.cooperation, educational training and
    talent training for NDL.

1993 ● Renamed to “National Nano Device Laboratories” and opened comprehensively for
    academic circle and industry to use.

1992 ● The class 10 clean room was operated officially to provide industry and academic circle with
    excellent device research services.

1988 ● The first national level semiconductor device laboratory was built and approved with the name
    as “National Sub Micron Device Laboratories” by Executive Yuan.