Press room
Annual Report

A New Milestone in Integrated Circuit Manufacturing Technology: Multiple Fin-Height FinFETs


The semiconductor industry is in a race to shrink integrated circuit (IC) size and improve performance. Using the most advanced existing semiconductor mass production technology, it is possible to produce approximately 100 million transistors on a chip of the size one square centimeter. The "multiple fin-height FinFET" process technology developed at the National Nano Device Laboratories (NDL), National Applied Research Laboratories allows more than 20 million transistors within the same area. By increasing the storage capacity of electronic products by 20%, or reducing manufacturing cost by 20%, this can sharply boost the international competitiveness of semiconductor manufacturers in Taiwan.

In conventional field-effect transistors (FETs), the gate (the purple part in the right diagram) can control Source-Drain current on only one side, forming a planar structure (upper diagram on the right). 
The gate on a "Fin Field-effect Transistor" (FinFET) has a three-dimensional forked shape resembling a fish's fin, and can control the Source-Drain current on three sides—the left, right, and top (central diagram on the right), forming a non-planar structure, respectively. 
NDL is a global leader in the development of FinFETs with multiple fin height. The different fin-height design concept allows different amount ofcurrents corresponding to appropriate channel height, which enables chip area to be shrunk further (lower diagram on the right).

We can use a single-story house, a home with a single floor area on one floor of a high-rise building, and homes with large, medium, and small areas on a floor of a high-rise building as metaphors for conventional field-effect transistors, single fin height FinFETs, and multiple fin height FinFETs. In a limited chip area, multiple fin height FinFETs allow large and small currents to live in appropriately-size houses, achieving optimal utilization of space.

Apart from reducing chip area, this study also reduced transistor power consumption, which increased the density of electronic elements that can be accommodated on a chip. Compared with a single fin-height FinFET, a multiple fin-height FinFET can reduce chip area by 20% (i.e., the number of chips that can be produced on a wafer with a single size can be increased by 20%), which can cut costs by 20% or increase chip storage capacity by 20%. The results of this study will have a tremendous impact on the development of the semiconductor industry, and the announcement of the study's results at the IEEE Symposia on VLSI Technology & Circuits held in Kyoto, Japan in mid-2013 attracted great attention, also prompting the  international journal IEEE Spectrum to publish a special report on the new technology.

The results of IC R&D over the past 20 years have generally conformed to the trend predicted by Moore's Law, which states that the density of transistors accommodated on a chip will double every 18-24 months. Because conventional planar FETs cannot be shrunk any further with physcial problems, novel FinFETs will be the main focus of future IC manufacturing R&D. The multiple fin-height FinFETs developed at NDL embody the innovative structural thinking that will be needed in the 3-D elements of the future, and have attracted attention throughout the industry. The research team has applied to patent this technology, which will be transferred to industry as quickly as possible.

The "non-planar element production service platform" unveiled this month by NDL will provide domestic researchers with a new tool for R&D of various types of prototype elements and process technologies, and will facilitate a seamless transition between forward-lookinFacts about field-effect transistorsg research at academic and research organizations and practical industrial processes, enabling research findings to effectively enhance the international competitiveness of Taiwan's semiconductor industry.


*The IEEE Symposia on VLSI Technology is a benchmark conference and forum allowing researchers from around the world in the fields of electronics and electrical engineering to announce their newest findings. The standards of papers presented at the conference are extremely high, and such prominent international semiconductor companies as TSMC, Intel, and Samsung pay close attention to this event. 
**IEEE Spectrum is the journal of the Institute of Electrical and Electronics Engineers (IEEE), which has over 420,000 members in more than 160 countries worldwide. Only the most important research findings in the fields of electronics and electrical engineering are reported in this journal.

Facts about field-effect transistors

Field-effect transistors (FETs) are electronic elements used to control current flow. If we use the analogy of a reservoir supplying water, the reservoir represents the FET's source (S), the outlet is the drain (D), and the valve controlling the flow of the water is the gate (G).

FinFETs are an innovative form of FET. In conventional planar FETs, the control current passing the gate is only controlled on one side of the current channel. But 
when the gate is only nanometers in length, it is very difficult to shut off the current. In a FinFET, the gate has a forked, three-dimensional structure, like a fish's tail, which allows it to control the circuit from three sides. This design can greatly alleviate the problem of current leakage, and facilitates the continuing efforts to make even smaller FETs.