R & D
Nano Device
Emerging Device
● Development of advanced complementary metal-oxide semiconductor device technology
Advances in semiconductor device technology mean the increasing miniaturization of devices reduce costs through increased density. Increasing miniaturization means that the gate dielectric must become thinner as well to supply sufficient drive current. When the thickness of the traditional SiO2 dielectric layer falls below 2nm, however, the tunneling effect generates massive gate leakage current. To overcome this problem, high-dielectric constant thin films have therefore drawn widespread research and discussion. High-dielectric constant thin films have a higher dielectric constant than traditional SiO2 thin films. It can achieve the same performance as an oxide layer with greater physical thickness, preventing tunneling currents while providing sufficient drive current. Overseas, Intel has formally applied high-dielectric constant gate technology to 45nm products. At the same time, the continued miniaturization of devices based silicon-based substrate will inevitably come up against more physical or material limit problems. Many materials with higher carrier mobility such as Ge and III-V family substrates are all being intensively studied to see if they can replace silicon channels. To prepare for the future, our team's research focus is on combining high-dielectric constant materials, metal gate structures and high-carrier mobility substrates as well as their attributes. We hope this will keep us on the forefront of future research into advanced devices.

● Silicides and low-RC interconnect technology
The general of silicides include low resistance as well as good thermal or chemical stability. MOSFET devices with silicide source/drain are now widely used in the manufacture of different nano MOSFET structures. While the so-called Schottky barrier formed by silicides and silicon channels suppressed leakage currents, it also imposes limits on on-current of the device. How to reduce contact resistance and increase on-current of the device is therefore one of the key technologies that semiconductor companies and technology research teams all around the world are actively working on. In response to future needs of nano devices, NDL is actively investing in improvements to current bottlenecks in silicide technology. By studying new materials, interface engineering, electrical properties, material and thermal stability, we hope to make further improvements to the nature of conventional silicide and enhance nano device performance. The multilevel interconnect has two problems that affect its performance. The first is the RC delay introduced by the metal wiring and dielectric layer. The second is cross talk between metal wiring. RC delay slows the speed of signal transmission, increases cross talk and causes higher power consumption. Shortening the wiring length reduces RC-delay but this requires an increasing multi-level wiring architecture that increases process complexity. The substitution of wiring metal with lower resistance and dielectric material with a lower dielectric constant effectively reduces RC delay and cross talk. To meet the need for low-dielectric materials by nano devices in the future, the NDL is now studying new materials, new processes as well as thermal stability and better mechanical properties in the hope of contributing to the current bottleneck in low-dielectric materials.

● Nano materials and device simulation
Support the development of nano devices by using advanced nano manufacturing techniques to conduct research into nano structures and nano materials. These materials and structures include silicon nanowire, silicon quantum dot, gold nano particle, and carbon nanotubes for use in Flash memory, PV cells, biosensors and other devices. Our goal is to pioneer research topics of interest as well as provide the academia with a sound R&D platform and experimental platform.
Our goal is to develop a simulation platform for next-generation nano devices based on semi-classical and quantum physics. Our focus includes planar, bi- gate, tri-gate and nanowire transistors. Our simulation model describes device performance based on energy and time-delay calculations. We also develop advanced modeling and simulation tools for the development of non- conventional CMOS devices.